In computer hardware, shared memory typically refers to a large block of random access memory that can be accessed by several different central processing units (CPUs) or other components in a multiple-processor computer system. For example, mobile phones often contain a baseband processor, media processor, and LCD controller, each of which may share a common memory area. The components of a multiple-processor system often need to share information. For example, the media processor of a mobile phone may run an operating system that interacts with the baseband processor to make a telephone call. As another example, the media processor may write information into a frame buffer of the LCD controller that describes an image to be displayed. The information sharing between components typically requires many different control and data interfaces. Control and data interfaces may be defined between each of the components and between the components and the shared memory. Moreover, there may be additional interfaces between each component using the shared memory for coordinating accesses of the shared memory.
In a typical memory device containing dynamic random access memory (DRAM), a component accessing the memory sends an activate (ACT) command to begin using the memory device. Memory is typically accessed by providing a row and column address, and a row address may accompany the ACT command. The ACT command causes the specified row of memory to be cached in a buffer where subsequent read commands can access (e.g., read and write) various columns of the memory data. When the component is finished with the data in the row, the component typically issues a precharge (PCG) command that causes the row data to be written back to the memory bank. This cycle repeats as the component accesses additional rows of the memory data.
One problem with a shared memory device is that components in a multi-processor architecture often need to share banks within the shared memory device. For example, one bank may be assigned to one component to complete a task and then another component when the task is complete. As another example, the components may use a bank to share information between components, and may need to coordinate so that each component can detect when it is safe to access the memory. If two components attempt to write to the memory at the same time data corruption can result by one component overwriting the information written by the other component. Similarly, if one component writes information for sharing with another component to the memory and the other component reads from the memory too soon, the reading component will read old information. There is therefore a need for an improved method of sharing banks of memory.